We have designed the hardware which calculates SigmaDelta for every window of input data. The audio data is applied to the hardware sample by sample. The SigmaDelta is calculated continuously. It is not yet very clear that how SigmaDelta is analyzed to distinguish whether there is any embedded data or not.

download the visio file

To explain more about the schematic presented in a visio file, Firstly, there is a FIFO memory. It gets a sample at the top and adds its effect to the current Sigmadelta and instead sends out the effect of the earliest sample in the FIFO memory after subtracting its effect. In other words, the hardware does not calculate the sigmadelta of every window separately but it considers the difference between two consequent samples and changes the sigmadelta. It can speed up the system more efficiently.
Secondly, there is a decoder. It gets 8-bit samples and based on its value selects the 2 appropriate registers. We have 2 sets of registers. one set to save A values(the decreasing differences) and another set to save B values( the increasing differences). If the input sample is even the hardware increases its related registers and if it is odd, it decreases them. For example, if the input sample is 54 then 54-55 register and 53-54 registers should be increased. (note that if the register has been negative this change should be applied inversely).To solve the problem which occurs when registers pass zero (and since only absolute value of registers are important) we have considered a special bit called "s" for every register. Based on "s" and the LSB bit of the sample the registers are being changed.
The logic circuit related to "s" and "LSB bit" are drawn in page 2 and is available by double-clicking the "UDgen" square. In fact, UDgen decides if the counter should be counting upward or downward.
Thirdly, the A registers are added as well as the B registers. Finally sum of As are subtracted from sum of Bs and the final SigmaDelta is calculated.